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- 1 - e05328 sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or ot herwise under any patents or other right . application circuits shown, if any, are typical examples illu strating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXA3355TQ gps down converter ic description the CXA3355TQ is an ic developed as a gps rf down converter. this ic realizes a reduction in the number of external par ts by integrating lna, image rejection mixer, if filter and pll/vco parts, such as inductor and variable capacitors. (applications: gps rf down converter ic) features ? includes all functions required for the gps down converter ? low voltage operation: v cc = 1.6 to 2.0v ? low current consumption (active mode): 11ma (typ. at v cc = 1.8v, if 1mhz) ? low current consumption (power save mode) < 1 a ? total gain 100db ? total nf 4.0db ? on-chip vco and pll ? selectable tcxo frequency ? on-chip lna (nf = 2.0db) ? image rejection mixer ? on-chip if filter, and an external filter c an be connected as an option for further band narrowing. ? 1-bit if output package 48-pin tqfp (plastic) structure sige bicmos monolithic ic
CXA3355TQ - 2 - absolute maximum ratings (ta = 25 c) recommended operating conditions ? supply voltage v cc 1 ?0.2 to +2.5 v v cc 2 ?0.2 to +3.6 v ? operating temperature topr ?40 to +85 c ? storage temperature tstg ?65 to +150 c ? supply voltage v cc 1 1.6 to 2.0 v v cc 2 1.6 to 3.3 v
CXA3355TQ - 3 - block diagram and pin configuration 17 18 15 14 13 16 19 20 21 22 23 24 44 43 42 47 48 46 45 41 40 39 38 37 27 28 29 30 25 26 31 32 33 34 35 36 10 9 8 7 12 11 6 5 4 3 2 1 1540fo = 1575.42mhz rf_amp if_amp1 if_amp1 mixer mixer bias lna 1536fo [1539fo] 4fo [fo] dmps mc pfd rc cp sc pll ctl if phase shifter if filter a/d converter if_amp2 90? 2 gnd (rf) rf_inp rf_inn gnd v cc 1 (lna) v cc 1 (lna) lna_out gnd gnd lna_in gnd (lna) gnd (lna) gnd (lna) nc nc vco_i c_vco gnd lpf v cc 1 (pll) gnd (pll) tcxo clk_out lt v cc 1 (rf) v cc 1 (rf) gnd (rf) testinp testinn testoutp testoutn v cc 1 (if) gnd (if) r_ext1 nc enable nc r_ext2 nc nc gnd nc c_ext data_out v cc 2 (if) gnd (if) data clk
CXA3355TQ - 4 - pin description pin no. symbol standard pin voltage [v] equivalent circuit description dc ac 1 r_ext2 1.16 ? external resistor connection. (bias) 2 nc ? ? normally leave open. 3 nc ? ? normally leave open. 4 nc ? ? normally leave open. 5gnd 0 ? gnd. 6 nc ? ? normally leave open. 7 c_ext 1.2 ? capacitor connection for canceling the offset. 8 data_out ? 1.8 vp-p data (if) output. 9v cc 2 (if) 1.8 ? if block v cc . 10 gnd (if) 0 ? if block gnd. 1 v cc 1 (if) gnd (if) 1k ? 7 v cc 1 (if) gnd (if) 8 v cc 2 (if) gnd (if)
CXA3355TQ - 5 - 11 data ? ? serial data input. 12 clk ? ? serial data clock input. 13 lt ? ? latch signal input. 14 clk_out 1.2 ? tcxo clock output. leave open when not using the tcxo clock. 15 tcxo ? ? reference frequency input. 16 gnd (pll) 0 ? pll block gnd. 17 v cc 1 (pll) 1.8 ? pll block v cc . 18 lpf ? ? pll loop filter connection. 19 gnd 0 ? gnd. pin no. symbol standard pin voltage [v] equivalent circuit description dc ac 12 11 13 v cc 1 (pll) gnd (pll) 14 v cc 2 (if) gnd (if) 15 v cc 1 (pll) gnd (pll) 18 v cc 1 (pll) gnd (pll)
CXA3355TQ - 6 - 20 c_vco ? ? capacitor connection for decoupling the vco bias circuit. 21 vco_i ? ? capacitor connection for decoupling the vco bias circuit. 22 nc ? ? normally leave open. 23 nc ? ? normally leave open. 24 gnd (lna) 0 ? lna block gnd. 25 gnd (lna) 0 ? lna block gnd. 26 gnd (lna) 0 ? lna block gnd. 27 lna_in 0.7 ? lna input. 30 lna_out 1.8 ? lna output. 28 gnd 0 ? gnd. 29 gnd 0 ? gnd. 31 v cc 1 (lna) 1.8 ? lna block v cc . 32 v cc 1 (lna) 1.8 ? lna block v cc . 33 gnd 0 ? gnd. pin no. symbol standard pin voltage [v] equivalent circuit description dc ac v cc 1 (rf) gnd (rf) 1k ? 20 21 v cc 1 (rf) gnd (rf) v cc 1 (lna) gnd (lna) 27 30
CXA3355TQ - 7 - 34 rf_inn ? ? rf amplifier input. 35 rf_inp ? ? 36 gnd (rf) 0 ? rf block gnd. 37 gnd (rf) 0 ? rf block gnd. 38 v cc 1 (rf) 1.8 ? rf block v cc . 39 v cc 1 (rf) 1.8 ? rf block v cc . 40 testinp 1.3 ? if signal input when using an external filter. 41 testinn 1.3 ? if signal input when using an external filter. 42 testoutp 0.5 ? if signal output when using an external filter. 43 testoutn 0.5 ? if signal output when using an external filter. 44 v cc 1 (if) 1.8 ? if block v cc . 45 gnd (if) 0 ? if block gnd. 46 nc ? ? normally leave open. pin no. symbol standard pin voltage [v] equivalent circuit description dc ac v cc 1 (rf) gnd (rf) 35 34 41 v cc 1 (if) gnd (if) 40 43 v cc 1 (if) gnd (if) 42
CXA3355TQ - 8 - 47 r_ext1 0.5 ? external resistor connection. (bias) 48 enable ? ? enable signal input. high (v_ih: 1.2v min.): active mode low (v_il: 0.2v max.): power save mode pin no. symbol standard pin voltage [v] equivalent circuit description dc ac 47 v cc 1 (if) gnd (if) 48 v cc 1 (if) gnd (if)
CXA3355TQ - 9 - electrical characteristics dc characteristics (v cc 1 = v cc 2 = 1.8v, ta = 25 c) note) fo mode uses the following power-on reset conditions. fo mode: tcxo = 18.414mhz, f lo = 1574.397mhz, if = 1.023mhz ac characteristics (v cc 1 = v cc 2 = 1.8v, ta = 25 c) note) fo mode uses the following power-on reset conditions. fo mode: tcxo = 18.414mhz, f lo = 1574.397mhz, if = 1.023mhz item symbol conditions min. typ. max. unit supply current 1 i cc 1 fo mode 7 11 15 ma supply current 2 i cc 2 power save mode ? 0.1 1 a item symbol conditions min. typ. max. unit total voltage gain g excluding the a/d converter 85 100 ? db image rejection ratio imrr frequency = 1.023mhz ? ?40 ?20 dbc lpf1 (fo mode) lpf1 @150khz normalized at 1.023mhz output level ?5 ? 4 db lpf2 (fo mode) lpf2 @2.046khz normalized at 1.023mhz output level ?13 ? 2 db lpf3 (fo mode) lpf3 @6mhz normalized at 1.023mhz output level ? ? ?13 db c/n 100k c/n if = fo, tcxo = 18.414mhz ? ?70 ?55 dbc/hz
CXA3355TQ - 10 - design reference value of operating conditions if output (data_out) (v cc 1 = v cc 2 = 1.8v, ta = 25 c) enable (v cc 1 = 1.8 0.2v, v cc 1 v cc 2 3.3v, ta = 25 c) power-on reset (v cc 1 = 1.8 0.2v, v cc 1 v cc 2 3.3v, ta = 25 c) tcxo (v cc 1 = v cc 2 = 1.8v, ta = 25 c) item symbol conditions min. typ. max. unit data_out rise time dtr pin 8 (data_out), 10 to 90%, load = 1m ? //13pf ?6?ns data_out fall time dtf pin 8 (data_out), 10 to 90%, load = 1m ? //13pf ?4?ns item symbol conditions min. typ. max. unit input voltage high level evih pin 48 (enable), input voltage high level threshold voltage 1.2 ? v cc 2 + 0.2 v input voltage low level evil pin 48 (enable), input voltage low level threshold voltage ?0.1 ? 0.2 v item symbol conditions min. typ. max. unit allowable rise time mtr enable and power supply (v cc 1, v cc 2) rise time for the power-on reset function to operate. note) use an enable and power supply (v cc 1, v cc 2) rise time of 100ms or less. ? ? 100 ms item symbol conditions min. typ. max. unit input level vtcxo pin 15 (tcxo) 0.2 0.6 1.2 vp-p clk_out rise time ctr pin 14 (clk_out), 10 to 90%, load = 1m ? //13pf ?6?ns clk_out fall time ctf pin 14 (clk_out), 10 to 90%, load = 1m ? //13pf ?4?ns
CXA3355TQ - 11 - threshold voltage (v cc 1 = 1.8 0.2v, v cc 1 v cc 2 3.3v, ta = 25 c) item symbol conditions min. typ. max. unit logic input voltage high level vih logic input pins = 11 (data), 12 (clk), 13 (lt) v cc 2 ? 0.2 ? v cc 2 + 0.2 v logic input voltage low level vil logic input pins = 11 (data), 12 (clk), 13 (lt) ?0.1 ? 0.2 v logic output voltage high level voh logic output pins = 8 (data_out), 14 (clk_out) v cc 2 ? 0.2 ? v cc 2v logic output voltage low level vol logic output pins = 8 (data_out), 14 (clk_out) 0?0.2v
CXA3355TQ - 12 - electrical characteristics measurement circuit note) 1. the rf block bypass capacitors should have excellent high frequency characteristics. 2. use parts with a tolerance of 1% for the following resistor elements. other parts should have a tolerance of 5%. ? pin 1 (r_ext2) ? pin 18 (lpf) ? pin 47 (r_ext1) 39k enable pin v cc 2 (if): active mode gnd: power save mode 0.1 0.1 10p 10n tcxo input level: 0.2 to 1.2vp-p clk_out v cc 1 (pll) v cc 1 (lna) v cc 1 (pll) v cc 2 (if) v cc 2 (if) v cc 1 (if) v cc 1 (rf) 10p 8p 100p 24k 12p 6p lna_in lna_out rf_in 3.3p 10n 3p 100p 1p 4.7p 50 ? matching condition data_out 18n 3.9n 3.3p 3.9n 1n 33k 1n buffer buffer testin testout bus control 16 17 14 13 15 18 19 20 21 22 23 24 44 43 42 41 48 47 46 45 40 39 38 37 27 28 29 30 25 26 31 32 33 34 35 36 10 9 8 7 11 12 6 5 4 3 2 1 gnd (rf) rf_inp rf_inn gnd v cc 1 (lna) v cc 1 (lna) lna_out gnd gnd lna_in gnd (lna) gnd (lna) gnd (lna) nc nc vco_i c_vco gnd lpf v cc 1 (pll) gnd (pll) tcxo clk_out lt v cc 1 (rf) v cc 1 (rf) gnd (rf) testinp testinn testoutp testoutn v cc 1 (if) gnd (if) r_ext1 nc enable nc r_ext2 nc nc gnd nc c_ext data_out v cc 2 (if) gnd (if) data clk
CXA3355TQ - 13 - initial settings the CXA3355TQ is initialized by setting the enable signal (pin 48) from low level to high level. the timing, etc. should sati sfy the conditions below. in addition, the tcxo frequency and if frequency combinations in the table below can be obtained by setting pin 11 (data), pin 12 (clk) and pin13 (lt) as shown in the table and then performing initialization. this eliminates the need for serial data setting. 1. during power-on the CXA3355TQ is initialized by simultaneously rising the power supplies and the enable signal (pin 48) during power-on. the power supply and enable (p in 48) rise time should be 100ms or less. in addition, the power supply (v cc 1, v cc 2) should rise simultaneously. 2. initialization after power-on after power-on, the CXA3355TQ is initialized by setting the enble signal (pin 48) to low level for 10ms or more and then setting it to high level. pin 11 (data) pin 12 (clk) pin 13 (lt) tcxo frequency [mhz] if frequency [mhz] gnd gnd gnd reserved reserved v cc 2 gnd gnd 18.414 1.023 v cc 2v cc 2 gnd 13 0.976 v cc 0.9 v cc 0.1 v cc gnd 100ms or less power supply, enable v cc gnd power supply v cc gnd 10ms or more 0.5 v cc enable
CXA3355TQ - 14 - serial data settings the CXA3355TQ can make the pll counter settings, perform tcxo_clk output, select the internal if filter, and use the test i/o circuit according to the serial data settings (3-wire bus control). the transfer bit length is 18 bits, and there are four addresses. the address is set by the a1 and a0 bits. the timing, etc. should satisfy the conditions below. serial data format mc (0 to 10): main counter frequency division value setting sc (0 to 4): swallow counter frequency division value setting rc (0 to 8): reference counter frequency division value setting clk: tcxo clk output (0: not output, 1: output) fil: internal filter selection (0: fo mode lpf, 1: reserved) tcl: if block test i/o control (0: when not using the test i/o circuit, 1: when using the test i/o circuit) ti (0 to 2): if block test input location setting to (0 to 2): if block test output location setting 0: logic input voltage low level 1: logic input voltage high level 18-bit data format serial data interface bus timing (3-wire bus control) (msb) a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 (lsb) d0 0 0 mc10 mc9 mc8 mc7 mc6 mc5 mc4 mc3 mc2 mc1 mc0 0 0 0 clk 0 0 1 sc4 sc3 sc2 sc1 sc0 rc8 rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 0 tcl 10ti2ti1ti0to2to1to000000 000fil0 1 1 mc10 mc9 mc8 mc7 mc6 mc5 mc4 mc3 mc2 mc1 mc0 0 0 0 clk 0 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data clk lt latch invalid data invalid data address data each data ? input data to all four addresses. time t sd t hd t hl t whlt clk data lt t low t high t sd = data setup time t hd = data hold time t low = low period of clk t high = high period of clk t sl = lt setup time t whlt = high pulse width (lt) t whlt 100ns t sd , t hd , t low , t high , t hl , t whlt 50ns
CXA3355TQ - 15 - description of functions test circuit the CXA3355TQ has a test circuit for test signal i/o. the test circuit is connected between each if block, and test i/o control can be performed by the serial data se ttings. the test circuit location, configuration and the serial data settings are as follows. test circuit location and configuration 0: logic input level low level 1: logic input level high level note) set the tcl register to ?1? when using or to ?0? when not using the test input circuit or the test output circuit. (see page 14.) serial data settings for test input selection serial data settings for test output selection ti2 ti1 ti0 test input to2 to1 to0 test output 0 0 0 normal operation 0 0 0 normal operation 0 0 1 ich if amp1 input 0 0 1 ich mixer output 0 1 0 qch if amp1 input 0 1 0 qch mixer output 0 1 1 not used. 0 1 1 not used. 1 0 0 not used. 1 0 0 not used. 1 0 1 if filter input 1 0 1 adder output 1 1 0 if amp2 input 1 1 0 if filter output 1 1 1 a/d converter input 1 1 1 if amp2 output 48 43 44 45 46 47 42 41 40 39 38 37 33 34 35 36 40 41 42 43 8 7 6 5 4 3 2 1 1540fo = 1575.42mhz local if_amp1 rf_amp if_amp1 mixer mixer "1i" "1q" if filter bias if phase shifter a/d converter if_amp2 90? "2" "3" "4" test input control test output control ? actual operation is differential, but only one side is shown. ? the inter-circuit connections are cut off during test input selection and test output selection. from each if block to each if block "1i": ich mixer output (ich if amp1 output) "1q": qch mixer output (qch if amp1 input) "2": adder input (if filter input) "3": if filter input (if amp2 input) "4": if amp2 output (a/d converter input)
CXA3355TQ - 16 - description of operation overview of operation this ic down-converts the gps (global positioning system) frequency of 1.57542ghz to fo (fo: 1.023mhz). the internal configuration is divided into the analog block, consisting of the amplifier, mixer and filters, and the digital block (including the comparator block and the control block), which forms pll. the analog block converts the frequency and amplifies the signal with the amplifier and the mixer, and eliminates undesired components with the filters. the digital block can switch the pll frequency division ratio in order to down convert the output signal to fo. 1. lna the gps signal that passes through the antenna is input to pin 27 via a matching circuit as shown in the figure below. the input signal is amplified by the lna, and then output from pin 30. always use matching circuits for the lna input pin (pin 27) and the lna output pin (pin 30), and match at 1.57542ghz. 2. rf amplifier, rf mixer, if phase shifter and adder the signal amplified by the lna passes through the saw filt er, and is then input to pin 34 via a matching circuit. the input signal is amplified by the rf amplifier, and then down-converted by the rf mixer to the fo (1.023mhz) i and q components. the if signal down-converted to the i and q components has the image component eliminated by the phase shifter and the adder, and is then input to the if filter. always use a matching circuit for the rf ampl ifier input pin (pin 34), and match at 1.57542ghz. 3. if filter the if signal that passed through the adder has the undesired components outside the band eliminated by the if filter. in fo mode the signal passes through only the lpf and is input to if amp2. set the serial data setting register fil to ?0? for fo mode (lpf), otherwise if output level is extremely low. in addition, an external filter can also be connected to this ic using pins 40 to 43. 35 34 30 27 lna 1540fo 0? 90? to if filter fo adder fo: 1.023mhz saw matching circuit 90? matching circuit matching circuit shifter to if amp2 from adder if filter
CXA3355TQ - 17 - 4. if amp2 and a/d converter the signal that passed through the if filter is amplifi ed by if amp2, converted into binary signal by the a/d converter, and then output from the data output pin (p in 8). the a/d converter performs sampling at the tcxo clk. in addition, the a/d converter output voltage high level is v cc 2 (1.6 to 3.3v), so a wide range of interfaces can be supported. 5. tcxo (pin 15) input the signal from the external oscillator to pin 15 via a capacitor as the reference signal. input frequencies from 10mhz to 26mhz are supported. the input signal level from the external oscillator should be 1.2vp-p or less (0.6vp-p typ., 0.2vp-p min.). this is also the same in power save mode. however, using the typical level of 0.6vp-p is recommended from the viewpoint of reducing disturbance waves to the receiving system. 6. tcxo clk output (pin 14) this ic can output tcxo clk from pin 14 according to the serial data setting. the output voltage high level is v cc 2 (1.6 to 3.3v), so a wide range of interface can be supported. set the serial data setting register clk to ?0? when not using tcxo clk, or to ?1? when using tcxo clk. (see page 13.) 7. pll/vco the pll is comprised by a vco, frequency divider and phase/frequency detector, as shown in the figure below, and incorporates an inductor, varactor. the loop filter is externally connected. use components that satisfy the required characteristics. serial data setting is unnecessary when this ic is used with the typical tcxo and if combinations set by the initial settings shown in page 12. this ic becomes unnecessary in the combination of typical tcxo and if by serial data initial setting. when making serial data settings, set counter frequency di vision values that satisfy the following equations. ? f vco = (m n + a) (f tcxo 2) r ? (f tcxo 2) r > 800khz ? n 3, r 3 f vco : vco oscillation frequency, f tcxo : tcxo frequency mc data = n, sc data = a, rc data = r, dmps data = m = 24 (fixed) 8. enable (pin 48) active mode and power save mode can be switched according to the level. ? high (v_ih: 1.2v min.): active mode ? low (v_ih: 0.2v max.): power save mode 18 15 mc 1/n sc 1/a rc 1/r pfd cp frequency division ratio (m n) + a tcxo (10mhz to 26mhz) to rf phase shifter loop filter 2 v cc 1 ? m = 24 vco dmps 1/m, 1/(m + 1)
CXA3355TQ - 18 - application circuit note) 1. this diagram shows the application circuit when the initial settings are made for 4fo mode. (see page 13.) 2. the rf block bypass capacitors should hav e excellent high frequency characteristics. 3. use parts with a tolerance of 1% for the following resistor elements. other parts should have a tolerance of 5%. ? pin 1 (r_ext2) ? pin 18 (lpf) ? pin 47 (r_ext1) enable pin vcc2 (if): active mode gnd: power save mode 0.1 0.1 10p 10n tcxo input level: 0.2 to 1.2vp-p v cc 1 (pll) v cc 1 (lna) saw filter v cc 1 (lna) v cc 1 (rf) v cc 1 (if) v cc 1 (pll) v cc 2 (if) v cc 1 (pll) v cc 2 (if) v cc 2 (if) v cc 1 (if) v cc 1 (rf) 10p 8p 100p 24k 12p 6p 3.3p 10n 3p 100p 1p 4.7p data_out 18n 3.9n 3.3p 3.9n 1n 39k 33k 1n 10n 10n 16 17 14 15 18 19 20 21 22 23 24 44 43 42 47 46 48 45 41 40 39 38 37 27 28 29 30 25 26 31 32 33 34 35 36 10 9 8 7 13 11 12 6 5 4 3 2 gnd (rf) rf_inp rf_inn gnd v cc 1 (lna) v cc 1 (lna) lna_out gnd gnd lna_in gnd (lna) gnd (lna) gnd (lna) nc nc vco_i c_vco gnd lpf v cc 1 (pll) gnd (pll) tcxo clk_out lt v cc 1 (rf) gnd (rf) v cc 1 (rf) testinp testinn testoutp testoutn v cc 1 (if) gnd (if) nc r_ext1 enable nc nc nc gnd nc c_ext data_out v cc 2 (if) gnd (if) data clk 0.1 1 v cc = 1.8v number of parts ?resistors: 3pcs ?capacitors: 20pcs ?inductors: 5pcs ?saw filter: 1pc 1 r_ext2 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
CXA3355TQ - 19 - supplement materials (example of representative characteristics) ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 0.1 1 10 100 frequency [mhz] filter response [db] fo upper spec (fo) lower spec (fo) ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 ?135 ?130 ?125 ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 lna_in input level [dbm] if amp2 output level [dbm] 5 10 15 20 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 vcc [v] icc [ma] fo 0 2 4 6 8 10 012345 frequency [mhz] total nf [db] ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 0.1 1 10 frequency [mhz] imrr [dbc] graph 1. i cc graph 2. total gain graph 5. filter response (normalized at 1.023mhz) v cc 1 = v cc 2 = 1.8v temp = 25?c graph 3. total nf graph 4. image rejection ratio fo mode v cc 1 = v cc 2 = 1.8v temp = 25?c v cc 1 = v cc 2 = 1.8v temp = 25?c v cc 1 = v cc 2 = 1.8v temp = 25?c
CXA3355TQ - 20 - ?100 ?90 ?80 ?70 ?60 ?50 ?40 0.01 0.1 1 frequency difference from the carrier [mhz] c/n [dbc/hz] ?85 ?80 ?75 ?70 ?65 ?60 lna_in of evb local leak [dbm] graph 6. local leak v cc 1 = v cc 2 = 1.8v temp = 25?c graph 7. c/n v cc 1 = v cc 2 = 1.8v temp = 25?c
CXA3355TQ - 21 - sony corporation package outline (unit: mm) sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin copper alloy package structure 48pin tqfp (plastic) 1 12 13 24 25 36 37 48 0.2 0.03 0.2g tqfp-48p-l01 p-tqfp48-7.0x7.0-0.5 (8.0) (0.5) a 1.2max 7.0 9.0 palladium plating 0.6 0.15 0? to 8? 0.1 0.05 detail a 0.08 0.5 0.1 s s b detail b :palladium 0.125 0.02 0.2 0.03 (0.5) 0.25 a b 0.2 s a b x4 0.2 s a b x4 s a b

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